A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects

Abstract

With the rapid advancements of deep submicron and nano technologies the dimension of a chip is ever shrinking. With continuous shrinking of chip dimensions, immense interconnects are associated on a die to satisfy high bandwidth requirements and make a network-on-chip (NoC) architecture prone to large number of interconnect faults. Therefore the reliability becomes a crucial issue for the communicating parties in a NoC communication fabric. This paper presents a packet address driven test strategy that diagnoses NoC interconnects experiencing stuck-at (stuck-at-0 and stuck-at-1) faults. The proposed strategy is scalable to all sizes and types of mesh NoCs and can be extended to other NoCs. The simulation is done on a number of mesh NoCs to establish the scalability. The simulation results show the performance measured in terms of test and fault coverages that can reach to 100% at the expense of few CPU clocks.