Thermal resistance degradation of alloy die attached power devices during thermal cycling

Abstract

Backside scanning acoustic tomography (SCAT) images have been correlated to alloy morphology (cross-section) and composition data (stochiometry) to model the /spl Theta//sub JC/ degradation for surface mounted device packaged power ICs as a function of the temperature cycling range. We find that an appropriate setting of the die attach process can suppress needle-shaped Cu/sub 3/Sn in favor of roughly spheroidal Cu/sub 6/Sn/sub 5/. We derived from the degradation of /spl Theta//sub JC/ during thermal cycling stress tests with different temperature swings, an acceleration factor which can be described by the Coffin-Manson law. The fitting parameter q in this formula is 9.35 for the new improved setting of the die attach process when the HSOP package is used. Finally, a maximum /spl Theta//sub JC/ degradation of 0.34 K/W based on the normal distribution approach results in a lifetime of 12 years. When a customer requires a maximum /spl Theta//sub JC/ of 2.0 K/W at the end of life, 50 years can be guaranteed.