Effects of parasitic fringe capacitance on threshold voltage of underlap DG-MOSFET

Abstract

A compact model for the effect of parasitic fringe capacitance on the threshold voltage of a gate to source/drain (S/D) underlapped double-gate (DG)-MOSFET is developed. The authors' model includes the effects of channel thickness, oxide thickness and dielectric constant of a MOSFET structure. A simple expression is derived for the fringe capacitance and the threshold voltage. In this model, we show the effect of fringe capacitance on the threshold voltage by varying the channel thickness, oxide thickness, and dielectric constant.