Jiaoyan Chen, D. Vasudevan, E. Popovici, M. Schellekens
{"title":"Reversible online BIST using bidirectional BILBO","authors":"Jiaoyan Chen, D. Vasudevan, E. Popovici, M. Schellekens","doi":"10.1145/1787275.1787333","DOIUrl":null,"url":null,"abstract":"Test generation for reversible circuits is currently gaining interest due to its feasibility towards quantum implementation and asymptotically zero-power dissipation. A novel BIST (Built-In-Self-Test) method for reversible circuits is proposed in this paper. New bidirectional D-latch and D-flipflop designs are introduced. A Reversible BILBO (Built-in-Logic-Block-Observer) based on conventional BILBO is designed to facilitate the BIST procedure. The complete test procedure is executed and experimental results are analyzed for both stuck at and missing gate faults (MGF) with 100% fault coverage.","PeriodicalId":151791,"journal":{"name":"Proceedings of the 7th ACM international conference on Computing frontiers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 7th ACM international conference on Computing frontiers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1787275.1787333","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Test generation for reversible circuits is currently gaining interest due to its feasibility towards quantum implementation and asymptotically zero-power dissipation. A novel BIST (Built-In-Self-Test) method for reversible circuits is proposed in this paper. New bidirectional D-latch and D-flipflop designs are introduced. A Reversible BILBO (Built-in-Logic-Block-Observer) based on conventional BILBO is designed to facilitate the BIST procedure. The complete test procedure is executed and experimental results are analyzed for both stuck at and missing gate faults (MGF) with 100% fault coverage.