Adaptive supply voltage and duty cycle controller for yield-power optimization of ICs

Abstract

With aggressive scaling of silicon technology, integrated circuits (ICs) yield has emerged as a prominent concern. Yield loss comes from timing problems induced by process variations introduced by inaccuracy in nano-scale CMOS fabrication. To address this concern, we have developed a system to assist in optimizing yield and power. The system consists of timing violation sensors, clock duty-cycle controllers, and dynamic voltage scaling techniques to avoid timing violations and to reduce the supply voltage as much as possible. By using failure probability maps, we evaluate the yield and performance enhancement of an example microprocessor system.