Design of a low power viterbi decoder for wireless communication applications

Abstract

In this paper, a novel low-power Viterbi decoder with soft decision is proposed. For the branch metric of the Viterbi decoder, our design employs a soft-decision method to improve its correction capability. In order to find the survivor path efficiently, we modify the classical Viterbi decoding algorithm into a new one. This new algorithm is similar to the register-exchange method with lower latency, but using RAM instead of register banks for recording the output bit-stream of the survivor path. Hence, our design can provide a low-power design. Finally, the chip of this design consumes about 28.6K gates using TSMC 0.18 μm CMOS technology. The power consumption of our chip is about 19.5mW at 100MHz.