Power gating technique for reducing leakage power in digital asynchronous GasP circuits

Abstract

There are multiple methods to reduce power consumption of digital circuits one of them is power gating. This paper introduces a new Power Gating technique for the GasP family of asynchronous circuits to achieve power savings. Large amount of power utilization in digital circuits is due to leakage current, as sub threshold conduction, junction leakage, and tunneling leakage through gate oxide. As per result from experiment, it is found that power gating is the most effective method to reduce sub threshold leakage. In power, gating there is a PMOS, a NMOS transistor is used to provide virtual power supply to block which is known as Virtual VDD and Virtual GND. NMOS, and PMOS transistor is known as sleep transistors. The power control logic turns on the power in anticipation of the receiving signal. The power control logic turns off the power when the circuit block is idle because either it is empty or pipeline is obstructed. GasP circuit make possible power gating is used in each stage. A latch is used in this article for storing the data coming from previous stage. This latch is power efficient because it drives only when necessary. It preserve its output and permits power gating.