{"title":"A PLL with high-speed operating discrete loop filter","authors":"Seong-Jin An, Young-Shig Choi","doi":"10.6109/JKIICE.2016.20.12.2326","DOIUrl":null,"url":null,"abstract":"In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator’s output signal. A switch controlled loop filter is introduced into the proposed PLL instead of a conventional 2 nd -order loop filter. Those three switches are controlled by the very high frequency output signal of voltage controlled oscillator. The switches are also controlled by UP/DN signals and ‘on/off’ depending the presence of UP/DN signals. A negative feedback functioned capacitor with a switch does make it possible to integrate the PLL into a single chip. The proposed PLL works stably even though a total of small 180pF capacitor used in the discrete loop filter. The proposed PLL has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.","PeriodicalId":136663,"journal":{"name":"The Journal of the Korean Institute of Information and Communication Engineering","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The Journal of the Korean Institute of Information and Communication Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.6109/JKIICE.2016.20.12.2326","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator’s output signal. A switch controlled loop filter is introduced into the proposed PLL instead of a conventional 2 nd -order loop filter. Those three switches are controlled by the very high frequency output signal of voltage controlled oscillator. The switches are also controlled by UP/DN signals and ‘on/off’ depending the presence of UP/DN signals. A negative feedback functioned capacitor with a switch does make it possible to integrate the PLL into a single chip. The proposed PLL works stably even though a total of small 180pF capacitor used in the discrete loop filter. The proposed PLL has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.