Implementation of a Modified Model-SRAM Using Tanner EDA

Abstract

Due to the increased demand of SRAM with large use of SRAM in System On-Chip, the oxide thickness has become a tough challenge in CMOS technology. The leakage power also affects the chip design process. Speed of SRAM and Power consumption are also taken care of for designing a chip. This article represents the simulation of 6T SRAM; Asymmetric SRAM cells using low power reduction techniques. All the simulations have been carried out on 180nm at Tanner EDA tool. In this article, SRAM cell will includes one more extra transistor that will control the overall capacitances during the write and read operation and will optimize the total capacitance that results in decrease in the power dissipation. The circuit verification is done on the Tanner tool, Schematic of the SRAM cell is designed on the S Edit and net list simulation done by using T-spice and waveforms are analyzed through the W-edit.