A Modified Reduced switch counts Multilevel DC link 3-phase Inverter using Half bridge Level Doubling (LDN) Network

Abstract

A modified reduce switched multilevel DC link (MLDCL) 3-phase Inverter with half-bridge level doubling (LDN) network is proposed and simulated in MATLAB/Simulink environment. Using this proposed topology, a 21-level per phase voltage & 37-level line to line voltage Inverter has developed using minimum number of semiconductor switches & isolated DC supplies. As total switch counts reduced, losses associated with the switches minimized during the operation of the Inverter. As a result, efficiency of the overall system has enhanced. A Capacitor is connected to the half- bridge LDN network. This capacitor does not deliver or consume any power from the source during the operation of the Inverter. It has the self balancing capability & does not require any closed loop control to maintain the constant voltage across the capacitor. To improve the power quality, level shifted multicarrier PWM technique has adapted. The 3rdharmonics injection technique has used to maximize the utilization of DC bus, as a result, the number of levels of line to line output voltage increases to 43 from 37. Simulation result verifies the proposed scheme.