Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance

Abstract

Conventional low bandwidth Phase lock loop uses an external Capacitor together with a big on chip ripple capacitor. A new architecture of a Phase lock loop is proposed which eliminates the need for an external capacitor. Also the value of the on chip capacitor is reduced drastically, reducing the chip size. The PLL architecture proposed uses very low power.