A Clock Synchronization Ramp Sloping Active Clamped PWM Circuit

Abstract

Due to current control characteristic may be lost when slope compensation is too large in a current PWM controller. A clock synchronization ramp sloping compensation method is presented in this paper. Firstly, a voltage-current circuit is used to convert the clock signal into a synchronous current ramp signal, and then the wave of PWM is produced by comparing it with the loop error. Moreover, the RS flip-flop stability is ensured from the aspects of circuit timing and circuit structure. External resistivity parameters and external voltage set the maximum duty ratio so that the circuit can avoid sub-harmonic oscillation. Using the delay circuit to delay the main power MOSFET (NMOS) signal rise edge and active clamp MOSFET (PMOS) signal fall edge, realize interactive drive time adjustment of active clamped circuit. A high voltage BCD process fabricates the designed circuit to satisfy the voltage requirement from 8V to 36V and prevents the generation of latch-up. Simulation and verification results show that the clock synchronous ramp sloping active clamp PWM circuit has a good load adjustment rate and high efficiency. The maximum duty cycle can reach 80%, and the efficiency reaches 90%.