{"title":"RNS reverse converters for moduli sets with dynamic ranges of 9n-bit","authors":"H. Pettenghi, R. Matos, A. S. Molahosseini","doi":"10.1109/LASCAS.2016.7451030","DOIUrl":null,"url":null,"abstract":"In this paper, we extend the traditional 3-moduli set {2n, 2n - 1, 2n+1}, with an equivalent 3n-bit dynamic range, and propose a moduli set extension with a maximum dynamic range of 9n and improve the parallelism according to the requirements. This paper also introduces a novel moduli set to design efficient reverse converters by using modular operations of the form 26n - 1 in order to achieve at most 9n-bit. Experimental results suggest that area reductions up to 65.61% and speed up of 2.38 can be obtained with our proposal in comparison with the best solutions existing in the state-of-the-art with the same DR. The proposed converter allows fewer bits per channel in comparison with the most efficient solutions with smaller dynamic ranges.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LASCAS.2016.7451030","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this paper, we extend the traditional 3-moduli set {2n, 2n - 1, 2n+1}, with an equivalent 3n-bit dynamic range, and propose a moduli set extension with a maximum dynamic range of 9n and improve the parallelism according to the requirements. This paper also introduces a novel moduli set to design efficient reverse converters by using modular operations of the form 26n - 1 in order to achieve at most 9n-bit. Experimental results suggest that area reductions up to 65.61% and speed up of 2.38 can be obtained with our proposal in comparison with the best solutions existing in the state-of-the-art with the same DR. The proposed converter allows fewer bits per channel in comparison with the most efficient solutions with smaller dynamic ranges.