A 28nm Configurable Asynchronous SNN Accelerator with Energy-Efficient Learning

Abstract

In this paper, we put forward an energy-efficient configurable asynchronous SNN accelerator for energy-constrained applications, which includes 256 neurons and 131K synapses with 8-bit fixed point weight. To achieve high energy efficiency and on-chip learning ability, we propose a sparse target propagation (S-TP) algorithm and design the accelerator with Click-based bundled-data asynchronous circuits. The SNN accelerator is implemented in 28nm CMOS process, and the post place and router (post-PAR) simulation results indicate that the SNN accelerator achieves on-chip learning with inference power efficiency of 3.97 pJ/SOP and 95.7% classification accuracy on NMNIST test dataset, which outperforms prior neuromorphic on-chip learning systems.