Active-mode leakage power optimization using state-preserving techniques

Abstract

As technology sizes shrink, the developers come upon a problem of leakage currents. Among the different power reduction approaches there are power gating and clock gating, which can significantly eliminate (cut down) components of power consumption. The combined use of these approaches shows great promise. In fact, this good idea poses challenges due to some difficulties in practical integration. First, there is a need in additional control logic and timing overheads appear. Secondly, the flip-flops need to be shut down during active-mode without any loss in logic states. We examine different state-preserving techniques that can retain data of flip-flops during the power gating. All presenting techniques can achieve leakage reduction in active mode of operation for combined approach.