{"title":"A 0.9–3.0 GHz fully integrated tunable CMOS power amplifier for multi-band transmitters","authors":"D. Imanishi, K. Okada, A. Matsuzawa","doi":"10.1109/ASSCC.2009.5357277","DOIUrl":null,"url":null,"abstract":"A tunable power amplifier (PA) from 0.9 GHz to 3.0 GHz is presented. This paper proposes an output impedance tuning method by using resistive feedback and a parallel resonance consisting of an inductor and a tunable capacitor array. The proposed multi-band PA can adjust the output impedance to 50 Ω over a wide frequency range, so external isolators following PAs can be eliminated. The PA is implemented by using a 0.18 μm CMOS process, and the supply voltage is 3.3 V. Over all of the frequency range, the PA realizes output return loss S22 of smaller than −10 dB, power gain of larger than 16 dB, output 1-dB compression point of larger than 17 dBm, and power added efficiency (PAE) at 1-dB compression point of larger than 10%.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357277","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 21
Abstract
A tunable power amplifier (PA) from 0.9 GHz to 3.0 GHz is presented. This paper proposes an output impedance tuning method by using resistive feedback and a parallel resonance consisting of an inductor and a tunable capacitor array. The proposed multi-band PA can adjust the output impedance to 50 Ω over a wide frequency range, so external isolators following PAs can be eliminated. The PA is implemented by using a 0.18 μm CMOS process, and the supply voltage is 3.3 V. Over all of the frequency range, the PA realizes output return loss S22 of smaller than −10 dB, power gain of larger than 16 dB, output 1-dB compression point of larger than 17 dBm, and power added efficiency (PAE) at 1-dB compression point of larger than 10%.