A VLSI architecture for difference picture-based dynamic scene analysis

Abstract

An efficient parallel architecture that exploits the parallelism and pipelining possible in the difference picture-based technique (IEEE Trans. on Pattern Analysis and Machi Intelligence, vol. PAMI-3, no.5, p.489-543, (1981); Computer, p.12-18, Aug. (1981)) is presented for dynamic scene analysis. Each processor is organized as a pipeline, and the processor architecture is simple enough that the motion detection and classification system can be implemented on a single VLSI chip. The proposed VLSI architecture and the design of the various components of the basic processor are described. VLSI chip implementation issues are discussed.<>