An Energy Efficient 32 Bit Approximate Dadda Multiplier

Abstract

In this paper, a 32-bit approximate Dadda Multiplier is implemented using 4:2 compressor. A Dadda Multiplier much alike to a Wallace Multiplier. The above multipliers are used to reduce the partial products but Dadda Multiplier is quite faster when compared to other multipliers as it requires few gates than Wallace Multiplier and thus leads to lower power consumption. The compressors used here has it’s own accuracy level in approximate mode with variable delay and less power consumption. The proposed multiplier can also perform exact operation but 1.5625% error for average case. Synopsys Design Compiler using SCL 180nm CMOS technology was used to evaluate the efficiency of the compressors in 32-bit Dadda Multiplier and compared with other 4, 8 and 16-bit Dadda multipliers. The comparative study results depicts around 59.5%, 54.5% and 14% decrease in power consumption with an area of 17504 µm2.