Inductance on silicon for sub-micron CMOS VLSI

Abstract

It has long been customary for silicon-based IC designers to restrict their attention to resistive and capacitive effects when considering circuits confined to the chip. The simple justification for this approach has been that typical "RC" time constants in this environment dwarf the "time of flight" of light across the distances involved. However, with the advent of large chips running at upwards of 100MHz, this assumption is called into question. Furthermore, due to the lossy nature of the silicon environment, the "time of flight" in question does not follow simply from the delay rate of light in silicon dioxide (i.e. 66ps/cm). In general, it is greater. This paper attempts to frame the problem and suggest design principles to deal with it. These principles have been used extensively in the design of a 200MHz 64-bit dual-issue CMOS microprocessor.