Area-time high level synthesis laws: theory and practice

M. Potkonjak, J. Rabaey
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引用次数: 3

Abstract

We introduce three AT DSP high level synthesis laws that relate different components of the area of ASIC implementation cost, namely foreground memory, execution units, and interconnect to the sampling period (available time). The laws state that: A=const, AT=const, and AT/sup 2/=const for the area of registers, execution units, and interconnect respectively. We validate the AT laws using case studies and statistical analysis of synthesis results of 80 real life designs. Several applications of the AT laws for development of high level synthesis tools are presented. Use of the AT high level synthesis laws as an effective method for encapsulation of high level synthesis knowledge is also studied, The effectiveness of the AT laws applications is documented on numerous designs.
区域-时间高级综合规律:理论与实践
我们介绍了三个AT DSP高级综合定律,它们与ASIC实现成本领域的不同组成部分有关,即前台内存,执行单元和互连到采样周期(可用时间)。法律规定:A=const, AT=const和AT/sup 2/=const分别用于寄存器、执行单元和互连区域。我们使用案例研究和80个实际设计的合成结果的统计分析来验证AT定律。介绍了AT定律在高级综合工具开发中的几种应用。本文还研究了利用AT高级综合规律作为封装高级综合知识的有效方法,并在许多设计中记录了AT规律应用的有效性。
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