A CNN Accelerator on FPGA with a Flexible Structure

Abstract

Most of the existing convolutional neural networks (CNNs) are based on PC software, which cannot meet the real-time, low power and miniaturization requirements of the systems. In this paper, a CNN accelerator with flexible structure based on Field-Programmable Gate Array (FPGA) is proposed to achieve recognition of MNIST handwritten numeric characters. The system adopts deep pipeline processing and optimizes inter-layer and intra-layer parallelism from two levels of coarse and fine granularity. In view of the similarity of convolution structure, this design adopts structured circuit, which can easily expand the number of layers and neurons. The classification throughput and inter-layer data throughput capability can be improved by rationally organizing the internal memory resources of the FPGA. Compared with the general CPU, it achieves 3 times acceleration at 50MHz frequency, while the power consumption is only 2% of the CPU. Finally performance and power consumption are compared with other accelerators by VGG16.