Logic synthesis of binary, carry-save and mixed-radix arithmetic for digital signal processing

Abstract

All the commercially available logic-synthesis tools currently use only (non-redundant) binary and two's complement number representations for representing the results of arithmetic operators. We analyze and compare silicon real-estate and throughput of word-parallel arithmetic circuits (add and shift type arithmetic) based on various redundant number representations and compare these results with the automatically optimized two's complement implementations. The literature on redundant number representations typically recommends radix-4 arithmetic for full-custom or a traditional semi-custom design style. We show that the radix-4 implementation is often not optimal for a logic-synthesis based semi-custom design style. Instead, a high-radix or a mixed-radix implementation (which we derive) should be considered.