Zuoliang Ning, B. Blalock, E.M. Nance, J. Oliver, R. Van Berg, P. O'connor, C. Britton
{"title":"A high voltage CCD Sensor Control Chip for the Large Synoptic Survey Telescope (LSST)","authors":"Zuoliang Ning, B. Blalock, E.M. Nance, J. Oliver, R. Van Berg, P. O'connor, C. Britton","doi":"10.1109/MWSCAS.2008.4616854","DOIUrl":null,"url":null,"abstract":"A Sensor Control Chip (SCC) that can drive a 20 V adjustable output voltage swing and a maximum output current of 100 mA has been developed to provide the required clock and bias signals for the Large Synoptic Survey Telescopepsilas CCD imagers. The prototype chip has been fabricated in a 0.8-mum BCD-SOI process, and is designed to operate down to 150 K. The circuit consists of current steering DACs followed by transimpedence operational amplifiers to control the rail voltages of the clock signals and bias voltages. The clocks are input to the SCC through LVDS receivers and converted internally to the required amplitude for driving the CCD. Design techniques will be presented along with room temperature and operational temperature test results obtained from prototype chips.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 51st Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2008.4616854","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A Sensor Control Chip (SCC) that can drive a 20 V adjustable output voltage swing and a maximum output current of 100 mA has been developed to provide the required clock and bias signals for the Large Synoptic Survey Telescopepsilas CCD imagers. The prototype chip has been fabricated in a 0.8-mum BCD-SOI process, and is designed to operate down to 150 K. The circuit consists of current steering DACs followed by transimpedence operational amplifiers to control the rail voltages of the clock signals and bias voltages. The clocks are input to the SCC through LVDS receivers and converted internally to the required amplitude for driving the CCD. Design techniques will be presented along with room temperature and operational temperature test results obtained from prototype chips.