B. Kleveland, Jeong-Hyeok Choi, J. Kumala, Pascal Adam, Patrick Chen, Rajesh Chopra, Antonio Cruz, R. B. David, Ashish Dixit, Sinan Doluca, Mark Hendrickson, Ben Lee, Ming Liu, M. J. Miller, Mike Morrison, B. C. Na, Jay Patel, Dipak K. Sikdar, M. Sporer, Clement Szeto, Anju Tsao, Jianguang Wang, Daniel Yau, Wesley Yu
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引用次数: 3
Abstract
We propose improving system availability by performing in-field repair at the chip level. This enables margining and detection of degrading memory cells before the user observes any errors. A 576 Mb embedded DRAM at 1.5 GHz in a 40nm CMOS technology achieves improved resilience to both aging memory cells and cells with variable retention time (VRT). Un-interrupted user access of 6 billion 72-bit read and write operations per second is maintained during background repair.
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