Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process

Ryuichi Nakajima, Kazuya Ioki, J. Furuta, Kazutoshi Kobayashi
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引用次数: 4

Abstract

We examined the radiation hardness of the several types of flip-flops fabricated in a 130 nm bulk process by alpha-ray irradiation tests and circuit simulation. The simulated $\alpha -$SER of FFs with the critical charge larger than 14 fC becomes 1/100 of that with the critical charge of 10 fC. We propose a radiation-hardened flip-flop minimizing area, delay, and power overheads with 1/100 lower $\alpha -$SER in a 130 nm bulk process. The radiation hardness is achieved by adding series transistors and wires with only less than 14% area, 7% delay, and 12% power overheads in order to increase the critical charge. Alpha-ray irradiation tests revealed that the proposed method can reduce soft error rates to 1/100.
在130 nm批量工艺中,α-SER降低1/100,最大限度地减少面积,功耗和延迟开销
采用α射线辐照试验和电路模拟的方法,研究了在130纳米体工艺中制备的几种类型人字拖的辐射硬度。临界电荷大于14 fC时的模拟$\alpha -$SER为临界电荷为10 fC时的1/100。我们提出了一种抗辐射触发器,在130纳米批量工艺中,将面积、延迟和功耗开销降至最小,降低了1/100的$\alpha -$SER。辐射硬度是通过增加串联晶体管和导线来实现的,只有小于14%的面积,7%的延迟和12%的功率开销,以增加临界电荷。α射线辐照试验表明,该方法可将软错误率降低到1/100。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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