A novel seven level inverter with reduced number of switches

Abstract

This paper deals with a novel seven level cascaded multilevel inverter. Almost all the drawbacks of the conventional multilevel inverters is rectified by the proposed topology. This topology uses less number of switches (particularly in higher levels) as compared with conventional topology, where it reduces the complexity and overall size of the system which in turn reduces the harmonics and cost of the entire system. Fewer switches will be conducting for specific time intervals so switching loss is also reduced in the proposed topology. A seven level inverter simulation is carried with the implementation of nearest level control. The proposal is validated by extensive simulation studies.