{"title":"Fault tolerant neural networks with hybrid redundancy","authors":"Lon-Chan Chu, B. Wah","doi":"10.1109/IJCNN.1990.137773","DOIUrl":null,"url":null,"abstract":"A fault-tolerant neural network with hybrid redundancy is proposed and analyzed. A hybrid redundancy is a combination of spatial redundancy, temporal redundancy, and coding. It is based on the homogeneity of both structures and operations of neurons. By storing multiple sets of weights in a processor and by recomputing the outputs of neurons with multiple processors, faults in the processors can be detected and corrected. This architecture can highly increase the reliability of a neural network so that a fairly large number of faulty neurons can be detected and that the outputs of these faulty neurons can be recovered. The redundancy of this architecture is fairly low if only certain critical neurons, such as output neurons, are implemented with this technique","PeriodicalId":385719,"journal":{"name":"1990 IJCNN International Joint Conference on Neural Networks","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"39","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1990 IJCNN International Joint Conference on Neural Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IJCNN.1990.137773","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 39
Abstract
A fault-tolerant neural network with hybrid redundancy is proposed and analyzed. A hybrid redundancy is a combination of spatial redundancy, temporal redundancy, and coding. It is based on the homogeneity of both structures and operations of neurons. By storing multiple sets of weights in a processor and by recomputing the outputs of neurons with multiple processors, faults in the processors can be detected and corrected. This architecture can highly increase the reliability of a neural network so that a fairly large number of faulty neurons can be detected and that the outputs of these faulty neurons can be recovered. The redundancy of this architecture is fairly low if only certain critical neurons, such as output neurons, are implemented with this technique