Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET

Abstract

A major effect of different measurement delay in seconds is revealed through quasi DC Stress Measure Stress experiments. We found that different delay of measurements in seconds contributed to different stress time needed to achieve target 10% degradation of Vth. The longer delay, the more time needed for the device to achieve 10% degradation of Vth. The effect on NBTI degradation is shown to be reliant on stress conditions (stress voltage, temperature) and device architecture (gate dimensions, gate oxide thickness). The NBTI lifetime was predicted by extrapolating lifetime to the nominal operating voltage from Time-to-Fail versus stress bias and oxide electric field plots. Both plots show that the lifetime of degradation parameter of Vth is lower compared to the lifetime of degradation parameter of Idsat.