A DSP48-Based Reconfigurable 2-D Convolver on FPGA

Abstract

Two-dimensional (2-D) convolution is a widely used operator exploited in image processing and computer vision. Many schemes of the FPGA-based 2-D convolver are focused on the buffer scheme and computational complexity. This paper optimizes the convolution unit from a unique perspective – underlying resource utilization, and presents a novel reconfigurable 2-D convolver. The purpose of this structure is to probe into the internal structure and resources of DSP blocks in FPGA and give full play to their computing power to complete convolution. This 2-D convolver can greatly reduce the consumption of logic resources without sacrificing the equivalent performance of convolution. The experiment results also demonstrate that this structure presents considerable adaptability to different sizes of images and kernels, making it suitable for various FPGA implementations.