An efficient packet fair queueing (PFQ) architecture for latency rate server

Abstract

The queuing/scheduling algorithm is one of the most important mechanisms to provide guaranteed quality of service (QoS) in high speed packet-switched networks. By computing the system virtual time and per packet/connection virtual start/finish time, a number of packet fair queueing (PFQ) algorithms are designed to simulate GPS (generalized processor sharing). The difference in computation complexity is due to the variable ways to compute system time. Many algorithms, including WFQ/WF/sup 2/Q, SCFQ, SPFQ, WF/sup 2/Q+, VC, etc., have been proposed to use different system virtual time (also known as system potential) function. This paper proves that all the latency-rate (LR) servers only need to calculate their system virtual times once per packet service time, no matter how many packet arrivals occur in this interval. Thus, it is a general scheme that benefits all the well-known LR PFQ algorithms.