Role of parasitic BJT in the design of DMOSFET

Abstract

Use of device simulation programs in teaching power semiconductor devices courses is illustrated. A design procedure for DMOSFET is outlined and use of simulation to analyze device behavior is illustrated. It is shown that the parasitic BJT plays a very important role and the device design should try to minimize it from the very beginning. Usefulness of the device simulation in the analysis of the device operation is demonstrated. Some of the common problems in using simulation are given and remedies provided.