32nm technology node Double-Gate SOI MOSFET using SiO2 gate stacks

Abstract

State of the art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the Ultra-Thin Silicon Body Double-Gate (UTB-DG) MOSFET. n-MOSFETs designed according to an original scaling strategy are simulated and the main figures of merit of the high-performance MOS transistor for digital applications are evaluated and compared to the requirements of the International Technology Roadmap for Semiconductors.The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field.