A bit-split byte-parallel string matching architecture

Abstract

String matching is one of hot spots in computer science. Many algorithms for string matching have been proposed, but designing an efficient and practical string matching architecture to satisfy high-speed data streaming is difficult and needs further study. In this paper we propose a high throughput configurable string matching architecture based on Aho-Corasick algorithm. The architecture can be realized by random-access memory (RAM) and basic logic elements instead of designing new dedicated chips. The bit-split technique is used to reduce the RAM size, and the byte-parallel technique is used to boost the throughput of the architecture. By the particular design and comprehensive experiments with 100MHz RAM chips, one piece of the architecture can achieve a throughput of up to 1.6Gbps by 2-byte-parallel input, and we can further boost the throughput by using multiple parallel architectures.