Advanced Process Modules for (sub-) 45nm Analog/RF CMOS - Technology Description and Modeling Challenges

2006 European Microwave Integrated Circuits Conference Pub Date : 2006-09-01 DOI:10.1109/EMICC.2006.282792

S. Decoutere, V. Subramanian, J. Loo, C. Gustin, B. Parvais, M. Dehan, A. Mercha

引用次数: 0

Abstract

The new process module and device architecture options emerging for (sub-) 45nm CMOS lead to both opportunities and challenges for analog/RF circuit design. A survey is given describing the advanced process modules for competing architectures (planar bulk CMOS versus FinFETS), for different gate stacks and mobility enhancement techniques. Challenges for compact modeling are identified

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用于(亚)45纳米模拟/射频CMOS的先进工艺模块-技术描述和建模挑战

新的工艺模块和器件架构选项出现在(亚)45纳米CMOS中，为模拟/RF电路设计带来了机遇和挑战。一项调查描述了竞争架构(平面体CMOS与finfet)的先进工艺模块，用于不同的栅极堆栈和迁移率增强技术。确定了紧凑建模的挑战

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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