Self-aligned ultra thin HfO/sub 2/ CMOS transistors with high quality CVD TaN gate electrode

Abstract

In this paper, we have demonstrated and characterized self-aligned, gate-first CVD TaN gate n- and p-MOS transistors with ultra thin (EOT=11/spl sim/12 /spl Aring/) CVD HfO/sub 2/ gate dielectrics. These transistors show no sign of gate deletion and excellent thermal stability after 1000/spl deg/C, 30 s N/sub 2/ anneal. Compared with PVD TaN devices, the CVD TaN/HfO/sub 2/ devices exhibit lower leakage current, smaller CV hysteresis, superior interface properties, higher transconductance, and superior electron and hole mobility.