Exploring the Potential of Error-permissive Communication in Multi-FPGA-based Edge Computing

Akram Ben Ahmed, Ryousei Takano, Takahiro Hirofuchi
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Abstract

In recent years, Edge Computing has been attracting a lot of attention as it has shown its ability to mitigate some issues found in Cloud Computing (e.g., high latency, centralization issues, programmability, etc.), Moving computation from the Cloud to the Edge has resulted in an exponential increase in the number of devices to be connected. With such an increase, interconnection has become a major design and performance factor, especially in terms of power efficiency. Thus, the question that a lot of research has been trying to answer is how to connect such devices in a power-efficient way while making sure to maintain high-performance and accuracy at the lowest cost. In this paper, we investigate the Error-permissive communication paradigm and its potential to answer the aforementioned question. In particular, we focus on the importance of using this paradigm on Multi-FPGA systems which have gained significant attention in Edge Computing and can be a good candidate for Error-permissive communication. We also present a preliminary evaluation of a novel concept to reduce the power consumption by undervolting the supply voltage of the serial transceivers, and we show its potential to reduce the total FPGA power consumption by up to 26%.
探索基于多fpga的边缘计算中容错通信的潜力
近年来,边缘计算吸引了大量的关注,因为它已经显示出它能够缓解云计算中发现的一些问题(例如,高延迟,集中化问题,可编程性等)。将计算从云计算转移到边缘导致要连接的设备数量呈指数级增长。随着这种增长,互连已成为一个主要的设计和性能因素,特别是在功率效率方面。因此,许多研究一直试图回答的问题是如何以一种节能的方式连接这些设备,同时确保以最低的成本保持高性能和准确性。在本文中,我们研究了允许错误的通信范式及其回答上述问题的潜力。特别是,我们专注于在多fpga系统上使用这种范式的重要性,这些系统在边缘计算中得到了极大的关注,并且可以成为容错通信的良好候选者。我们还对通过降低串行收发器的供电电压来降低功耗的新概念进行了初步评估,并展示了其将FPGA总功耗降低高达26%的潜力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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