Sleepy lector: A novel approach for leakage reduction in DSM technology

Abstract

Leakage power consumption is a major contribution of total power dissipation in Deep Sub-Micron (DSM) technology for CMOS circuit design. In this paper we have proposed a Novel circuit technique known as “Sleepy LECTOR” which mitigates various type of leakage current in DSM regime. In proposed technique we insert p-type sleep transistor above pull up network, and n-type sleep transistor below pull down network, which rail of from Vdd to GND for reduction of leakage power. Another Leakage controlled transistor (LCTs) PMOS and NMOS inserted between pull up and pull down network, these transistors are always near cut OFF voltage which increases the path resistance from supply to ground reducing leakage power, it is self controlling transistor. Lector transistors produce the stacking effect and producing high resistance path from Vdd to ground. By using Sleep transistors we can turn off the circuit by rail from power supply (Vdd) during standby mode for reduction of leakage power. The proposed circuit technique reduces the Power with respect to basic NAND gate 37.69%, 83.93%, N AND gate with sleep 79.15%, 86.69%, NAND gate with Lector 36.79%, 12.05% respectively in 65nm and 45nm Process Technology.