A 0.2 to 1.7 GHz low-jitter integer-N QPLL for power efficient direct digital RF modulator

Abstract

A wide lock-range supply regulated integer-N QPLL is proposed to reduce power consumption of the wideband direct digital RF modulator. SINC roll-off characteristic for supply noise of the inverter-based ring-VCOs in frequency domain maximizes loop bandwidth of the wide lock-range PLL. The proposed charge pump keeps loop bandwidth for all integer-N divider ratio. The fabricated QPLL achieves 0.2 to 1.7GHz lock rage with 10MHz bandwidth, 100MHz reference, and on-chip loop filter. The RMS jitter is 1.28ps, maximum supply noise sensitivity is 0.34rad/V, and power consumption is 13.2mW from 1V supply at 1.7GHz PLL output frequency. The active area is 0.064mm2.