Memristor based full subtractor

Abstract

Extending the use of memristor technology beyond memory to computing has recently received a lot of attention. Memristor-based logic design is a new approach that aims to make computing systems more efficient. In this paper, a one-bit full subtractor is implemented using MAND, MOR, and XOR gates. The proposed circuit's simulation results, which include all of the above gates, have been published. In comparison to a typical circuit, the proposed circuit has less area, delay but has larger power dissipation when compared with CNTFET due to high memristance. The circuit was simulated in cadence virtuoso with the VTEAM memristor model.