Analysis of ultra-low voltage digital circuits over process variations

Abstract

Ultra-low voltage electronics is a subject that introduces unique issues. Problems such as process variation adversely affect digital electronics at ultra-low voltages. Signal integrity and systematic timing strongly influence low-voltage digital designs because of the low static noise margin. Candidate solutions include Schmitt-trigger gate design and asynchronous paradigm such as the NULL Convention Logic. Four gate libraries are constructed for comparison between static CMOS and Schmitt-trigger gate design, and between synchronous and asynchronous logic gates. A small test circuit is implemented to measure success rate, active energy, leakage power, and threshold under process variation. Results show that process variation strongly affects ultra-low voltage electronics and that Schmitt-trigger gate design and NULL Convention Logic are effective solutions for deep subthreshold operation.