Analog BIST generator for ADC testing

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2001-10-24 DOI:10.1109/DFTVS.2001.966787

S. Bernard, F. Azaïs, Y. Bertrand, M. Renovell

引用次数: 13

Abstract

In the context of analog BIST for A/D converters, this paper presents an implementation of an on-chip ramp generator. It is demonstrated that the proposed original adaptive scheme allows the internal generation of a highly sawtooth signal with a very precise control of the signal amplitude. In addition, the implementation of the adaptive ramp generator exhibits a very low silicon area.

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用于ADC测试的模拟BIST发生器

在A/D转换器模拟BIST的背景下，本文提出了一种片上斜坡发生器的实现方法。结果表明，所提出的原始自适应方案允许内部产生高度锯齿信号，并对信号幅度进行非常精确的控制。此外，自适应斜坡发生器的实现显示出非常低的硅面积。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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