Design and Implementation of Switched Capacitor Cascaded Multilevel Inverter for Symmetric Sequence

Abstract

The new nine-level multilevel inverter (MLI) topology that utilizes Unipolar Pulse Width Modulation is proposed. It provides maximum output voltage level while using the minimum dc source and switches. The concept is implemented on a 9-level symmetric MLI. Multi carrier unipolar pulse width modulation technique is adopted to create the switching pulses. Total harmonic distortion (THD) simulations for both voltage and current waveforms have been performed. Comparison is performed for different topologies with proposed topology. The simulation tests for new proposed MLI is done in a MATLAB/Simulink. The newly proposed topology of 9 level MLI is implemented in hardware.