Carry select and input select adder for late arriving data

Abstract

An adder is described which is optimized for the case of one of its inputs having a skewed arrival time. If the least significant bits of either of the operands arrives last, a conventional adder will not be able to execute concurrently with any of the prior computation. This paper shows a design which takes advantage of the early arriving bits and performs early computation of the sum. The adder has been fabricated and is part of the exponent unit of a future mainframe computer.