Chaotic processing in parallel speed independent architectures

Abstract

Mathematical and computer simulation of chaotic processes in parallel architectures with speed independent logical units by means of method of chaotic relaxation with delay is considered. This method allows to imitate effectively the fulfillment of chaotic computing process in parallel architecture. Behavior of network consisting of interacting logical units is considered. We use the circuit for defining the end moment of transient processes in logical units. For computer simulation the solution of the Dirichlet problem for the Laplace differential equation on a rectangular domain in R/sup 2/ was chosen. Numerical simulation of this problem, using networks with speed independent logical units is presented.