In Orbit Single Event Upset Detection and Configuration Memory Scrubbing of Virtex-5QV FPGA

Abstract

This paper presents a method to detect and correct single event upsets likely to occur in the configuration memory of SRAM-based FPGAs especially in a spaceborne scenario, specifically addressing the Virtex-5QV FPGAs. As compared to DWC or TMR techniques, the scrubbing approach is instead preferred; the internal type being superior due to self-contained configuration interfaces. A Finite State Machine based controller is used to control the detection of memory upsets and subsequently to effect the scrubbing process. Internal Configuration Access Port primitive is used to read the configuration memory frames and an Error Correction Code primitive used to detect & locate the single bit error location inside a frame. Hardware implementation of the proposed technique is carried out and the simulation results presented. Pulsing diagrams indicate successful SEU detection and subsequent scrubbing through the PRGRAM_B pin of the FPGA, that may be invoked by telecommand on-board.