Short-circuit Analysis using a Parallel QBF Solver

Abstract

The analysis of input conditions that may cause a short-circuit in a logic circuit has recently become a critical issue, due to the potential presence of parasitic circuit elements after layout. This analysis is strongly related to the problem of determining paths in a graph whose edges are defined by related logic functions. Logic circuits can be modeled as a generic graph, where edges are a logic function of static input variable combinations, representing transistors that act like logic switches. The solution to this problem must address a complex SAT-problem involving an extensive inspection of all possible paths between two nodes, the power supply and ground. We describe an efficient method, based on a Quantified Boolean Formula (QBF) model, that solves this problem in an incremental way. We propose a parallel implementation for multi-core shared-memory machines. The Espresso logic minimization tool was critical to keep the size of the intermediate logic functions manageable. In order to be able to use this tool in parallel, we developed a thread-safe version of Espresso and have made it available to the community. The proposed solution was validated against a set of benchmarks that show the effectiveness of our parallel implementation, allowing to address instances of transistor-level circuits for a wide range of inputs and internal nodes efficiently.