G. Murdoch, M. O'Toole, G. Marti, A. Pokhrel, D. Tsvetanova, S. Decoster, S. Kundu, Y. Oniki, A. Thiam, Q. T. Le, O. Pedreira, A. Lesniewska, G. Martinez-Alanis, S. Park, Z. Tokei
{"title":"First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP","authors":"G. Murdoch, M. O'Toole, G. Marti, A. Pokhrel, D. Tsvetanova, S. Decoster, S. Kundu, Y. Oniki, A. Thiam, Q. T. Le, O. Pedreira, A. Lesniewska, G. Martinez-Alanis, S. Park, Z. Tokei","doi":"10.1109/vlsitechnologyandcir46769.2022.9830150","DOIUrl":null,"url":null,"abstract":"In this paper we demonstrate the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects from 26 to 18nm metal pitch (MP), fabricated on 300mm wafers. We have developed a novel integration flow, using the principle of subtractive etching of Ru, on 2 subsequent metal levels. Using structures with programmed overlay shift, we demonstrate the functionality of a fully self-aligned via process which results in working devices with placement errors of up to 5nm. Furthermore, we show via-to-line breakdown field > 9MV/cm, confirming FSAV.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830150","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
In this paper we demonstrate the functionality of a semi-damascene integration scheme with fully self-aligned vias (FSAV) for interconnects from 26 to 18nm metal pitch (MP), fabricated on 300mm wafers. We have developed a novel integration flow, using the principle of subtractive etching of Ru, on 2 subsequent metal levels. Using structures with programmed overlay shift, we demonstrate the functionality of a fully self-aligned via process which results in working devices with placement errors of up to 5nm. Furthermore, we show via-to-line breakdown field > 9MV/cm, confirming FSAV.