Hardware Software Co-Simulation of Obfuscated 128-Bit AES Algorithm for Image Processing Applications

Abstract

With the rapid advancement of communication technology, secure data transfer has become the primary concern for every communication system. Advanced Encryption Standard (AES) has been proved to be useful and effective for providing high security to the image processing applications. In this paper, Active Fixed Hardware Obfuscation based secure 128-bit AES algorithm is proposed for improving the security aspects of image data transfer. The proposed method adopts the classic framework of Xilinx System Generator (XSG) which uses Vivado 2016.2 and MATLAB 2015b. Hardware Software Co-simulation is done using XSG on Xilinx 7000 SoC FPGA ZedBoard. Extensive simulation results using various test cases demonstrate the effectiveness and robustness of the proposed method. Security analysis results in terms of Histogram analysis, Adjacent Pixel Auto-Correlation Test and Information Entropy Test show that the encryption quality of the proposed method reaches the current state of the arts. Simulation results show that the proposed method offers 1.49% of area overhead with respect to original AES design. The proposed method exhibits throughput of 5.48Gbps.