FPGA implementation of a low power, processor-independent and reusable System-on-Chip platform

Abstract

In order to achieve low cost and reduced time to market goals ASIC and Embedded system designers have always struggled to come up with a basic platform, which once built and verified can easily be reconfigured and reused. Moreover they are also been challenged with compatibility issues of their designs with different processors. In this paper, we have presented a System-on-Chip (SoC) platform architecture, which once built can be modified for different processors with minimal effort. Using a bus architecture that allows easy addition and removal of various modules, our proposed SoC can be reconfigured and reused as a platform for various projects. Moreover, we have also included those modules in our chip which are the building blocks of almost all ASIC and embedded applications. Finally, implementation parameters of this SoC on Xilinx FPGA are reported.