Precise current matching charge pump for digital phase locked loop

Abstract

In digital phase locked loop cascode structured charge pump is proposed with current mismatch less than 0.01%. Steady state error in digital phase locked loop can be minimized by reducing current mismatch. The rail to rail operational amplifier and cascode current source circuit is employed to reduce the mismatch between charging and discharging current. The operational amplifier has high gain of 90dB. The proposed charge pump is designed, simulated and verified at power supply of 1.8V in TSMC 90nm CMOS technology.